Really apologize ...only 2 tickets left
Published: Thu, 03/01/18
Hi Thanks for being a loyal email subscriber. We appreciate hearing from you. Let us know if you ever have any questions.I am afraid, this is your…
VLSI System Design
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15 seats left..48 hours to enroll and claim free course
Published: Wed, 02/28/18
Hi Ever wondered how does a planned chip looks like? Well, above image is what you will be looking for. This way, you can get an estimate of you core…
60 hours to enroll & claim 1 course for FREE on Udemy
Published: Wed, 02/28/18
Hi Did you know there is no standard definition for GPIO’s? That’s the whole point of designing an SOC. Figuring out what things you are going to…
72 hours to go...Do you want to configure your own SoC?
Published: Tue, 02/27/18
Hi Did you know there is no standard definition for GPIO’s? That’s the whole point of designing an SOC. Figuring out what things you are going to…
4 days to enroll and claim 1 FREE course
Published: Tue, 02/27/18
Hi Did you know that for getting signals between 2 domains, level-shift down is a simple function, all you need to use is one of your digital buffers…
5 days to enroll and claim FREE course
Published: Mon, 02/26/18
Hi Did you know you can model a display using simple verilog test-bench, just like a UART? Did you know, you can plan your SoC online while at home?…
First and Largest ever webinar on full chip SoC design - Mar 3...
Published: Sun, 02/25/18
Hi Below is the agenda of the webinar which is happening on Mar 3, 9am to 1pm IST. This is the largest ever webinar happening on full chip SoC design,…
Life of Chip Designer...
Published: Sat, 02/24/18
Hi We just finished an amazing dry-run and it looks perfect for someone who wants to know in and out of chip design, right from SoC planning to RTL…
From VLSI to System Design (SoC) - The choice of SPI
Published: Thu, 02/22/18
Hi (Read this blog till end, if you want to move from VLSI to System Design)I started as Physical Design Engineer, moved to STA lead and stayed there…
Congratulations on successfully completing TL-Verilog assignment
Published: Thu, 02/22/18
Hi Please join me to congratulate below people for successfully completing the 'Certification Challenge' given by Steve during "Pipe-lining RISC-V…