Hi
Below is the agenda of the webinar which is happening on Mar 3, 9am to 1pm IST.
This is the largest ever webinar happening on full chip SoC design, that has never happened in the past. Have you ever seen a webinar where you plug and play with IP's
and design a chip of your specifications, verify your chip, synthesize, PNR and DRC/LVS. I haven't.
History is in the making and I welcome you to be a part of it. Here's the registration link:
Agenda:
(1) Introduction
(people)
(2) Introduction (efabless)
(3) Introduction (topic: Designing and verifying a RISC-V SoC)
(4) Agenda (topic outline)
(5) Login, efabless marketplace
(6) Marketplace overview
(7) CloudV overview
(8) Open Galaxy overview
(9) Raven SoC overview
(10) Catalog download Raven SoC
(11) Run-through of Raven files:
(A) picorv32
(B) raven_spi
(C) raven_soc
(D) digital peripheral (UART, flash controller)
(E) memory (SRAM)
(F) analog peripheral (ADC, DAC, POR, etc.)
(G) padframe
(12) Further description of SoC and choice of
connections between blocks
(13) Memory map description
(14) Top-level connections: padframe, level shifters, multiplexers
(15) Testbench C code
(16) Testbench verilog
code
(17) Makefile run-through
(18) Running testbench series (GPIO, ADC, DAC, UART)
(19) Example: Create a new testbench to test bandgap voltage
and use bandgap as reference to test the comparator.
(20) Example: Run the new testbench and verify operation.
(21) Overview of synthesis process
(22) Challenge: Add a general-purpose timer/counter module to raven_soc
(A) driven from selectable sources:
(i) master clock
(ii) crystal clock
(iii) external clock
(iv) RC oscillator output
(B) 32 bits
(C) Timer output routed to GPIO or
interrupt
(D) Counter output memory mapped
(E) Control values are the amount to add to the counter per
clock cycle and the value at which to toggle the timer output.
(F) One-shot or continuous
(G) Continuous mode may restart at zero or wrap
around
