Hi
Ever wondered how does a planned chip looks like? Well, above image is what you will be looking for. This way, you can get an estimate of you core and die area. A chip (just like city) once planned well, makes it easy for place and route. The only task which remains in above image is to route it. Its
just like planning roads for a city. The big blocks or IP's can be thought of buildings or complexes
Many people had questions about IP's. Many people had queries about chip integration. Many people had queries about RISC-V SoC application. This webinar answers is all. I welcome you all to my webinar on Mar 3, on how to design a RISC-V SoC, with Raven chip being an application, which can be used for popular IOT's
Here's
the registration link (Last 48 hours to enroll and claim one of my online courses for FREE on Udemy): (only 15 seats remaining)
It’s easy..Send me the ticket confirmation email and claim one of my below 19 courses on Udemy for FREE. So at price of 1 you
get 2…
- VLSI - Essential concepts and detailed interview guide
- VSD - Clock tree synthesis – Part 1
- VSD - Signal Integrity
- VSD - RISCV: Instruction set architecture – Part 1a
- VSD - Physical design flow
- VSD - Circuit design and SPICE simulations – Part 1
- VSD - Static timing analysis – Part 1
- VSD - Circuit design and SPICE simulations – Part 2
- VSD - Clock tree synthesis – Part 2
- VSD
- Custom layout
- VSD - Static timing analysis – Part 2
- VSD - Library characterization and modelling – Part 1
- VSD - Static timing analysis Webinar
- VSD - TCL programming – Part 1
- VSD - TCL programming – Part 2
- VSD - RISCV: Instruction set architecture – Part 1b
- VSD - Timing ECO Webinar
- VSD - Physical design webinar using EDA tool "Proton"
- VSD - Pipe-lining RISC-V with Transaction-Level
Verilog
Enroll and rise above, by being a Core SoC designer and build your own datasheet. All the best, and I will see you in webinar...
Happy Learning...
