Hi
Did you know that for getting signals between 2 domains, level-shift down is a simple function, all you need to use is one of your digital buffers (eg. above image
BU_3VX2)?
Its using a digital buffer from 3.3v std cell set, but you want to set the power supply for that at 1.8V. In the verilog, it doesn’t mention what voltage supply it is on a digital cell. So that may have to be checked
manually to make sure its correct.
Did you know that level-shift up is much more complicated thing? Its not something which you get by putting in a digital standard cell set. So, you have to make a cell for this. You give different voltage supplies on both sides (see below eg.). You need to use any of these cells to get supply from 1.8v to 3.3v
Like above, there are many more critical things that needs to be taken care while design a System on Chip (SoC). Something which goes beyond Physical design, RTL design, STA, Verification. Do you want to learn how to SoC
Design?
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