Sky130 Tapeout Workshop 2/6 - RTL Design and synthesis using Verilog
Published: Wed, 08/25/21
Hi After you have implemented your specs using a high level verilog language like TL-Verilog, the ne t step is to convert this to standard verilog…
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Published: Wed, 08/25/21
Hi After you have implemented your specs using a high level verilog language like TL-Verilog, the ne t step is to convert this to standard verilog…
Published: Sun, 08/22/21
Hi Does the above image motivates you? We had a 8th grade (13yr old) student who had joined RISC-V workshop last year and built his own RISC-V CPU…
Published: Fri, 08/20/21
Hi Just a reminder - RISC-V workshop registration closes in 3days This workshop has been the most effective RISC-V workshop so far, and reason is the…
Published: Wed, 08/18/21
Hi One message yesterday afternoon and another one today morning. So proud to see such messages when day begins. Really charges you up to do something…
Published: Wed, 08/18/21
Hi I know you might be thinking, what's the use of this workshop when there are so many free webinars and courses already over the web about RISC-V?…
Published: Tue, 08/17/21
Hi VSD is proud to announce a series of high-intensity lab-based RTL2GDS VLSI tapeout based workshops from August to September to October - specially…
Published: Mon, 08/09/21
This is how time flies. So don't wait for right time, because it never comes. just go ahead and do it now Hi We are in 8th month of this year, and we…
Published: Sat, 08/07/21
Hi Image shows a snippet of plethora of lab e periments which you will be doing during the workshop. This is just a reminder that registration for…
Published: Thu, 08/05/21
Hi This one mega VLSI tapeout workshop connects its all - basics, theory, tools, labs, opensource, DRC, LVS, tapeout - one workshop built for all…
Published: Tue, 08/03/21
Hi Toughest Semiconductor Workshop on planet - Physical Verification using Skywater 130nm technology has now been simplified and ready for deployment.