VSD delivered 1st online analog tapeout workshop using Sky130
Published: Sun, 08/01/21
Hi Ever heard of a 2-days online analog IP design and tapeout workshop? Ever heard that tapeout programs were even possible in a short span of 2-days?…
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This month - 12hrs left for all VSD VLSI courses at Rs. 360
Published: Sat, 07/31/21
Hey This is a gentle reminder for this months discount cycle. 12hours left to get all VSD VLSI online courses at Rs.360. Here are the links: All VLSI…
- Study these PLL specs - Last 12hours
Published: Thu, 07/29/21
Hi The above image are a snippet of PLL specification which we will be targeting for 2-days workshop starting from 31st August. The workshop is on…
Last 1 day -, this is how we taped-out PLL chip
Published: Wed, 07/28/21
Hi Sharing a snippet from out workshop recording session. This is just to show you how easy it is these days to tape-out a chip. Though we took about…
Tapeout - The Ultimate goal of VLSI engineer - Last 48 hrs
Published: Tue, 07/27/21
Hi Imagine yourself building the above in 2-days, from specifications to circuit to GDSII? Though it took us close to a year to tape-out PLL IP, but…
First time - Tapeout workshop on PLL using Sky130
Published: Mon, 07/26/21
Hi For the first time 2-day silicon ready, tape-out oriented workshop ONLY for students at an academic pricing of $25 (the lowest price point for VSD…
Last 9 hours - Mixed-signal RISC-V based SoC on FPGA course at Rs. 360
Published: Sat, 07/24/21
Pictures from LIVE FPGA webinar - 200+ participants from around the world joined this one...Sorry for the cricket bat at background. Sometimes, it's a…
Last4 hours for FPGA free webinar registration
Published: Fri, 07/23/21
Hi Registration for VSD Free Webinar - Mi ed-signal RISC-V based SoC on FPGA closes in 4 hours Here's the registration link:…
VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA
Published: Sat, 07/17/21
Hi This 60-min webinar helps you get started with a basic mi ed-signal FPGA flow, which can be e tended to any comple SoC. VSD and RedwoodEDA conducts…
Last 6 hours for HDP on vsdsram and RISC-V for NMOS modelling
Published: Thu, 07/15/21
Hi While all project are being taken up, 2 high visibility and possibly tape-out based ASIC projects are open to fill. In case you are interested, we…