For the first time 2-day silicon ready, tape-out oriented workshop ONLY for students at an academic pricing of $25 (the lowest price point for VSD workshops)
Date - 31st July and 1st August, 2021
Phase-Locked Loop(PLL) IC design on Open-Source Google-Skywater 130nm
This basic overview of Phase-Locked Loop IC design on Open-Source Google-Skywater 130nm node, takes an intuitive approach to designing a simple PLL with extraordinarily little math and without diving into complex frequency domain analysis or control system theory. The tools that will be used are Ngspice and Magic. These tools will be briefly covered, and no prior knowledge of these tools is required to take this course
This ULTIMATE workshop will help to bring on an early knowledge about tapeout, which is the final goal of any VLSI engineer or VLSI student
Recommended audience -
1) Any student who wants to take a very basic design from circuit to layout to tapeout and get a feel of how chips are designed and manufactured in industry (from basics)
2) Any Physical design professional who wants to know the end-to-end steps and process of IPs which he/she instantiates in floorplan, but never had a chance to deep-dive into IP
3) Any fresher, looking for a clear flow about start-end journey of a VLSI engineer (with hands-on labs)
Curriculum
Day 1 – PLL Theory and Lab setup
- Introduction to PLL
- Introduction to Phase Frequency Detector
- Introduction to Charge Pump
- Introduction to VCO and Frequency Divider
- Tool setup and design flow
- Introduction to PDK, specifications and pre-layout circuits
- Circuit design simulation tool - Ngspice Setup
- Layout design tool - Magic Setup
Day 2 – PLL Labs and post-layout simulations
- PLL components circuit design
- PLL components circuit simulations
- Steps to combine PLL sub-circuits and PLL full design simulation
- Troubleshooting steps
- Layout design
- Layout Walkthrough
- Parasitics extraction
- Post Layout simulations
- Steps to combine layouts
- Tapeout theory
- Tapeout labs
