After you have implemented your specs using a high level verilog language like TL-Verilog, the next step is to convert this to standard verilog language and synthesize using a foundry technology node. In our case, we will be using 130nm opensource pdk by Skywater. Now there is a catch - if the design is not written or extracted in the right way, you might just blow up your chip area, and hence
power. Before we even move to physical design, it's important to estimate if chip area is optimal, which is why you need the right techniques to analyze and code your RTL.
One can design a counter or one can design an optimized counter. Did you see the difference? That's where the "RTL design and synthesis using Sky130" workshop comes in. This workshop is built by decades of years of experience who expect VLSI aspirants to know RTL design fundamentals hands-on and not just books.
This workshop has been an eye-opener for all participants in the past as they were able to optimize their own circuits by 3X - it's a big number. Why is it a big number? Attend the workshop and find out by yourself. Here's the registration link which closes in 5-days. No late entries
This workshop is not the end. It will be followed by further workshops, which are listed in the above image and we will let you know about all of them very soon. Stay tuned
