RISC-V workshop registration closes in 3-days

Published: Fri, 08/20/21

Just a reminder - RISC-V workshop registration closes in 3days

This workshop has been the most effective RISC-V workshop so far, and reason is the content (see below). Its kind of high intensity umbrella training for RISC-V, which carves your future path in this area. Not sure if anybody has ever explained pipe-lining CPU design in the way, its explained in this workshop. A snippet of this workshop is shown in above image

Workshop details and content

Registration link-

https://www.vlsisystemdesign.com/riscv-based-myth/

A beginner level 5-day workshop on “RISC-V based MYTH” (24hrs x 5days on VSD-IAT platform)

When we say, “beginner level”, by end of workshop you will understand
• RISC-V specs
• RISC-V software
• How to implement RISC-V basic specs using TL-Verilog
• Simulate your own RISC-V core
*In short, you are going to write RTL and build RISC-V core on your own*

Workshop Day wise Content :

Day 1 : Introduction to RISC-V ISA and GNU compiler tool-chain

Introduction to RISC-V basic keywords
Labwork for RISC-V software tool-chain
Integer number representation
Signed and unsigned arithmetic operations

Day 2: Introduction to ABI and basic verification flow

Application Binary interface (ABI)
Lab work using ABI function calls
Basic verification flow using iverilog

Day 3: Digital Logic with TL-Verilog and Makerchip

Combinational logic in TL-Verilog using Makerchip
Sequential and pipelined logic
Validity
Hierarchy

Day 4: Basic RISC-V CPU micro-architecture

Micro-architecture and testbench for a simple RISC-V CPU
Fetch, decode, and execute logic
RISC-V control logic

Day 5: Complete Pipelined RISC-V CPU micro-architecture/store

Pipelining the CPU
Load and store instructions and memory
Completing the RISC-V CPU
Wrap-up and future opportunities

Many people have been asking VSD for a workshop on how to do RTL coding – Well, there you go.