RISC-V 32-bit Instruction Type Decode logic design in 120sec
Published: Tue, 06/01/21
RISC-V based MYTH (Microprocessor for You in Thirty Hours) – VLSI System Design Hi Just imagine what all things you can do in RISC-V MYTH 5-day…
VLSI System Design
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RISC-V CPU core in 90 sec !!
Published: Sun, 05/30/21
RISC-V based MYTH (Microprocessor for You in Thirty Hours) – VLSI System Design From C program -> RISC-V ISA -> Basic MUX -> Calculator -> 3-cycle…
Registration - Verilog RTL design/synthesis using sky130 - ends in 15hrs
Published: Sun, 05/23/21
Hi Ready for a 5-day high intensity hands-on workshop on "Verilog RTL design and Synthesis using Sky130"? Well, registration ends in 15hrs. If you…
Verilog RTL Design and synthesis using sky130 - last 2 days
Published: Sat, 05/22/21
Hi Many of you have asked for "Verilog RTL Design and synthesis using sky130" 5-day workshop curriculum. So, here's the details about the same (Its…
Last 1 hour for DAC IP Layout Design Free Webinar registration
Published: Fri, 05/21/21
Hi Since the webinar starts early today, the registration for FREE webinar closes in 1hour. If you have registered, you will receive email invite in…
10-bit DAC Analog IP Layout Design - Free Webinar
Published: Thu, 05/20/21
VSD Intern – 10-bit DAC Analog IP Layout Design And here's the last part of 3-series webinar on 10bit DAC IP design - This time, its LIVE Layout using…
[Last 6 hours] - DAC Circuit design webinar at Rs.360
Published: Wed, 05/19/21
Hi This is a gentle reminder that DAC Circuit design webinar online course will be available for Rs.360 for ne t 6 hours as shown in above image as…
Verilog RTL design and synthesis workshop - FAQs
Published: Tue, 05/18/21
RTL design and synthesis using Verilog with SKY130 Technology, 26 - 30 May, 2021 Frequently Asked Questions What are the registration fees? It is…
Most awaited workshop - Verilog RTL design and synthesis with Sky130
Published: Mon, 05/17/21
Hi Finally, after 7 months of pure dedication and hard-work, VSD is proud to announce the most awaited and most effective VSD-IAT 5-day workshop -…
VSD - Committed to future of open-source silicon
Published: Sat, 05/15/21
Hi Another masterpiece by Harshitha Basavaraju on DAC IP circuit design webinar using Xschem, Sky130 PDKs and ngspice. VSD is really proud of having…