Hi
Finally, after 7 months of pure dedication and hard-work, VSD is proud to announce the most awaited and most effective VSD-IAT 5-day workshop - "Basic RTL Verilog design and synthesis using Sky130 PDKs" which will happen from 26th -30th May. It has 70% labs on cloud
It was very carefully curated to make sure all freshers and 2nd/3rd/4th year engineering students get early knowledge about, not only just VLSI, but also are aware on fundamental principles under which industry prefers their RTL Verilog designs to be in. It was structured after speaking to close to 80 RTL designers and synthesis engineers, and understanding the way they model their designs in Verilog
And you know what? The problem statements and labs for this workshop are derived from direct interview questions by top VLSI company recruiters. So, this time, make sure you work super hard and clarify all your fundamentals about RTL design and synthesis using verilog. While making of this course, we had many RTL designs which gave surprising waveforms and we learned, how simple techniques can optimize your synthesis results.
You might want to learn that too. So, here's the registration link for the same. Last date of registration 24th May.
Target number of participants - 50
We can extend if you really need it, else we plan to stick to 50 participants
All the best and happy learning
