Verilog RTL Design and synthesis using sky130

Verilog RTL Design and synthesis using sky130 - last 2 days

Published: Sat, 05/22/21

Many of you have asked for "Verilog RTL Design and synthesis using sky130" 5-day workshop curriculum. So, here's the details about the same (Its updated in workshop website as well)

Workshop Registration link- (Registration closes in 2-days)

https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/

Workshop Day wise Content :

Day 1 - Introduction to Verilog RTL design and Synthesis

Introduction to open-source simulator iverilog
Labs using iverilog and gtkwave
Introduction to Yosys and Logic synthesis
Labs using Yosys and Sky130 PDKs

Day 2 - Timing libs, hierarchical vs flat synthesis and efficient flop coding styles

Introduction to timing .libs
Hierarchical vs Flat Synthesis
Various Flop Coding Styles and optimization

Day 3 - Combinational and sequential optmizations

Introduction to optimizations
Combinational logic optimizations
Sequential logic optimizations
Sequential optimzations for unused outputs

Day 4 - GLS, blocking vs non-blocking and Synthesis-Simulation mismatch

GLS, Synthesis-Simulation mismatch and Blocking/Non-blocking statements
Labs on GLS and Synthesis-Simulation Mismatch
Labs on synth-sim mismatch for blocking statement

Day 5 - Optimization in synthesis

If Case constructs
Labs on "Incomplete If Case"
Labs on "Incomplete overlapping Case"
for loop and for generate
Labs on "for loop" and "for generate"

All the best and happy learning