Upcoming VLSI workshop - Register in 2 steps [LAST 36 HOURS]
Published: Sun, 05/24/20
Hi There has been many queries about registration process for upcoming "RISC-V based SoC design using open-source EDA tools" workshop. Many of you…
VLSI System Design
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VSD VLSI workshop - Cloud is OLD, Intelligence in Next-Gen
Published: Sat, 05/23/20
Hi There has been a lot of queries about the platform and learning cycle for VSD upcoming workshop on "RISC-V based SoC design using open-source EDA"…
VSD-IAT: RISC-V based SoC design using open-source EDA
Published: Fri, 05/22/20
Hi Due to increasing system-on-chip design comple ity and tight time-to-market requirements, virtual learning platform (VSD-IAT) solution are current…
RISC-V based SoC and Open-source EDA – All automated
Published: Wed, 05/20/20
Hi Welcome to Ne t-Gen VSD trainings. It’s finally here for all of you – RISC-V based SoC, open-source EDA, Physical Design, Custom Layout, STA,…
Finally, DFT webinar is here...
Published: Sun, 05/17/20
Hi And finally, DFT webinar is here 18th May 7pm IST - In almost all our workshops, courses, webinars, we have been asked about DFT, and I always…
VSD is now “Intelligent VSD”
Published: Tue, 05/12/20
Hi After 9-years of e tensive research on VLSI students learning patterns and multiple 5-days workshop with students and professionals all over world,…
Opensource IP Bank – That is OUR internship program
Published: Fri, 05/01/20
Hi Finally, it is out – VSD has its own internship program with loads of fun learning and career growth. The day, like 4 years back, when we had…
Circuit design and signal integrity
Published: Sat, 04/25/20
Hi As observed in yesterday's Jatana Sir webinar, I had shared some below images which displayed impacts of CMOS scaling. These images are taken from…
Are you scaling down?
Published: Wed, 04/22/20
Hi Are you shifting technology from 180nm to sub-100nm? Are you scaling down ? You will get e posed to unseen issues and that's what today's 7:30pm…
Webinar - Components in Standard CMOS Process
Published: Wed, 04/15/20
Hi The more you enter SoC design, the more you realise the importance of passive components, the more you understand the importance of mi ed-signal…