Hi

Welcome to Next-Gen VSD trainings.

It’s finally here for all of you – RISC-V based SoC, open-source EDA, Physical Design, Custom Layout, STA, ngspice and Library characterization – All of them automated and connected in a single workshop platform, happening from 27^th May to 31^st May.

Here is a list of top basic questions that this workshop (and below image) will answer for you:

1. What is RISC-V? Is it a processor? Is it an architecture? Is it a micro-architecture?
2. What is VLSI? Which field should I be targeting?
3. What is digital VLSI and analog VLSI?
4. What is SoC design? What is Physical design? Are they same or different?
5. What is STA? How is it connected to Physical design? How does it impact RISC-V based SoC?
6. How is RISC-V based SoC and CMOS connected?
7. How does a bad CMOS circuit design impact a chip and hence its functionality?
8. How do I enter VLSI? Which is the best field in VLSI?
9. What is the duration and timings for workshop? Is it IST only? Is it for college students only?
10. What is the cost of the 5-day workshop? Can we design a full chip using open-source EDA tools?

These are some real problem statements, which are technical and non-technical. And that is what the next workshop on “RISC-V based SoC design workshop using open-source EDA tools” addresses.

Good news is – Anyone from any part of the world at any time-zones can join. It is open 24hrs between 27^th May to 31^st May. So, you can enter and exit whenever you are comfortable

Here is the link for more details on this workshop – Last day to register – 24^th May

https://www.vlsisystemdesign.com/upcoming-event/

Target number of students – only 100 (due to security reasons)

NIT Patna were first one’s to do a 5-day workshop using this platform and responses has been amazing

IMPORTANT NOTE – Many people missed to register for our previous webinar, either due to late registration or due to full registration seats. So, if you have decided to learn VLSI from scratch, then better book your seat soon.