VSD-IAT: RISC-V based SoC design using open-source EDA

Published: Fri, 05/22/20

Due to increasing system-on-chip design complexity and tight time-to-market requirements, virtual learning platform (VSD-IAT) solution are current demand to bridge the skilling process while working on those designs for majority of engineers.

As research pushes for better performance for SoC design, virtual platforms solve one of today’s biggest challenges in these systems: learn concepts, open source hands-on designing labs and acquiring analyzing methods before the real time designs are available, enables IP design and analyzing skills. Virtual platforms model the hardware architecture in the form of a simulator, including processors, memories, and standard blocks. They enable engineers to start developing and analyzing the design substantially earlier than has been possible in the past.

What is VSD-IAT?

VSD-IAT is expertly built training platform and is suited for designer requirements. Semiconductor companies understand the value of training automation and Engineer performance enhancement, and do not need to be convinced of the impact of a virtual platform for learning. VSD trainings are quick, relevant, and easy to access from any device at any time zone

Why VSD-IAT workshops?

Over 50K+ users trust VSD VLSI based workshops for last 7 years. VSD has been conducting workshops over a variety of topics semi-conductor like RISC-V, Embedded UVM, SoC design, Physical Implementation, Sign-off analysis, and Physical Verification. With VSD workshops, you can

Explore all RISC-V and VLSI concepts using open-source tools
Zero restrictions on using platform across all time-zones
Custom made content by VSD experts, based on recent ISA and VLSI trends and technologies
Workshop design methods gives Freedom to explore new design after workshop on the open source tools

About upcoming RISC-V based SoC design workshop:

Building a chip is like building a city...

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.

After a successful SoC planning, we take the chip forward and implement using end-to-end opensource EDA tools, and all on VSD-IAT cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.

The big question How is this possible? Welcome to upcoming workshop on “RISC-V based SoC design using open-source EDA”

Objectives and detailed curriculum:

At the end of each day of workshop, you should be able to achieve below:

Day 1: Study and review various components of RISC-V based SoC, familiarity with terminologies of IC design components, introduction to RISC-V, starting RISC-V SoC Reference design and get familiar to open-source EDA tools

Day 2: Understand importance of good floorplan vs bad floorplan and introduction to library cells, chip floor planning considerations, library binding and placement, cell design and characterization flows, and general timing characterization parameters

Day 3: Design and characterize one library cell using Magic Layout tool and ngspice, labs for CMOS inverter ngspice simulations, art of layout using Euler’s path plus stick diagram, labs for Magic and post-layout ngspice simulations and inception of Layout – CMOS fabrication process

Day 4: Pre-layout timing analysis and importance of good clock tree, Timing modelling using delay tables, Timing analysis with ideal clocks, Clock tree synthesis and signal integrity, Timing analysis with real clocks

Day 5: Final steps for RTL2GDS, Routing and design rule check (DRC), PNR interactive flow tutorial and post-route STA

Prerequisites:

We have custom made this course, so anyone with basic digital design knowledge can attend this workshop. Prior working to RISC-V SoC design and open-source EDA tools is not required

Open-source EDA tools used:

Below tools are silicon Proven for Raven which is XFAB-180nm RISC-V based chip, taped out by Efabless Corp. Pvt. Ltd.

1) Yosys for RTL synthesis

2) Qflow for RTL2GDS

3) Magic VLSI Layout tool

4) OpenSTA for Static timing analysis

5) Ngspice for SPICE simulations

Workshop Date & Timings – 27^th May to 31^st May (24hrs x5days)

Registration link:

https://www.vlsisystemdesign.com/upcoming-event/