RTL design, synthesis, PNR - Back2back workshops
Published: Tue, 06/15/21
Hi Its placements and appraisal time. So buckle up Two back-2-back 10-days workshops which now completes entire flow from Verilog RTL design to…
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VSD Partners with FOSSEE, IIT Bombay for eSim Marathon
Published: Wed, 06/09/21
Hi Great Opportunity by FOSSEE, IIT Bombay (and it's free) FOSSEE, IIT Bombay, along with VLSI System Design (VSD) Corp.Pvt. Ltd is organizing this…
Final call - RISC-V 5-day workshop
Published: Mon, 06/07/21
Hi If you have already registered for the workshop, you will receive your lab login details details on 8th June, so stay tuned to your registered…
24hrs left for RISC-V MYTH workshop registration
Published: Sun, 06/06/21
Hi Registration for pipe-lined RISC-V MYTH workshop closes in 24hrs https://www.vlsisystemdesign.com/riscv-based-myth/ Here's the curriculum: Workshop…
Last 3-days - Logic gates to RISC-V CPU in 50 sec
Published: Fri, 06/04/21
Hi - Registration closes in 3-days From logic gates to RISC-V CPU in 50 sec - This time, without music. The reason we cover logic gates is to bring…
[5-days left] RISC-V MYTH Workshop registration
Published: Wed, 06/02/21
TIME IS TICKING AWAY! Last 5-days left for RISC-V MYTH Workshop registration RISC-V Workshop Snippets
RISC-V 32-bit Instruction Type Decode logic design in 120sec
Published: Tue, 06/01/21
RISC-V based MYTH (Microprocessor for You in Thirty Hours) – VLSI System Design Hi Just imagine what all things you can do in RISC-V MYTH 5-day…
RISC-V CPU core in 90 sec !!
Published: Sun, 05/30/21
RISC-V based MYTH (Microprocessor for You in Thirty Hours) – VLSI System Design From C program -> RISC-V ISA -> Basic MUX -> Calculator -> 3-cycle…
Registration - Verilog RTL design/synthesis using sky130 - ends in 15hrs
Published: Sun, 05/23/21
Hi Ready for a 5-day high intensity hands-on workshop on "Verilog RTL design and Synthesis using Sky130"? Well, registration ends in 15hrs. If you…
Verilog RTL Design and synthesis using sky130 - last 2 days
Published: Sat, 05/22/21
Hi Many of you have asked for "Verilog RTL Design and synthesis using sky130" 5-day workshop curriculum. So, here's the details about the same (Its…