Hi
Here's the curriculum:
Workshop Day wise Content :
Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain
- Introduction to RISC-V basic keywords
- Labwork for RISC-V software toolchain
- Integer number representation
- Signed and unsigned arithmetic operations
Day 2: Introduction to ABI and basic verification flow
- Application Binary interface (ABI)
- Lab work using ABI function calls
- Basic verification flow using iverilog
Day 3: Digital Logic with TL-Verilog and Makerchip
- Combinational logic in TL-Verilog using Makerchip
- Sequential and pipelined logic
- Validity
- Hierarchy
Day 4: Basic RISC-V CPU micro-architecture
- Microarchitecture and testbench for a simple RISC-V CPU
- Fetch, decode, and execute logic
- RISC-V control logic
Day 5: Complete Pipelined RISC-V CPU micro-architecture/store
- Pipelining the CPU
- Load and store instructions and memory
- Completing the RISC-V CPU
- Wrap-up and future opportunities
Many people have been asking VSD for a workshop on how to do RTL coding – Well, there you go.
In meantime, take a look at single stage RISC-V core. All the best and see you in workshop
