That's why I love CMOS logic !!
Published: Fri, 11/06/15
It's so robust... I can give you 4 instances of this1) Vary PMOS width size to its ma imum, keeping NMOS width constant and with couple of SPICE…
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Published: Fri, 11/06/15
It's so robust... I can give you 4 instances of this1) Vary PMOS width size to its ma imum, keeping NMOS width constant and with couple of SPICE…
Published: Tue, 10/27/15
- When I launched my course on "Circuit design and SPICE simulations" with just 5 videos and a pre-launch offer, there were many eye-brows raised…
Published: Tue, 10/20/15
-- "I've learned so much from my mistakes .... I'm thinking of making a few more"I have 5 courses on marketplace, and they at-most cover everything…
Published: Tue, 10/13/15
Hi We were looking for a solution for below scenario, and you will be amazed to see, how an 'Universal Gate' solves the below problem (of-course, at…
Published: Mon, 10/05/15
Hi And here's the solution to the problem posted in my previous article. 'AND gate itself'. If you observe carefully, you tie one of the inputs of an…
Published: Tue, 09/29/15
Hi While trying to build a clock tree which is power aware, let's go back a step ahead and look, what are the top observations for a clock network,…
Published: Thu, 09/24/15
Hi How about saving some power for the below clock tree network ?It's tricky and if we go with the right approach, we might end up saving almost…
Published: Sat, 09/19/15
Hi I have been getting this query, about, how to learn VLSI topic (especially back-end) from scratch, and there you go. I have arranged the videos and…
Published: Fri, 09/18/15
Hi Long time ... since my last post .... Reason : Hopefully, I have given enough time for you to get hold on my previous 3 posts. Now, that you have…
Published: Thu, 09/10/15
Hi If you have read through my previous posts on the above topic, things have seriously become interesting over here. I mean, isn't that e citing, we…