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Published: Thu, 04/22/21
Hi Want to e perience how a fresher can enter into Analog VLSI design? Want to e perience a fresher viewpoint towards Bandgap Reference design using…
Published: Tue, 04/13/21
Hi Just a reminder - The below email e pires in ne t 4hrs. Enroll and start generating memory IPs using OpenRAM. All the best and happy learning…
Published: Mon, 04/12/21
Hi Hopefully all of you attended the webinar on "OpenRAM configuration for 4kB SRAM design". It was a complete hands-on LIVE session, with so many…
Published: Wed, 04/07/21
Hi Welcome to VSD Intern Webinar on "OpenRAM configuration for 4kB SRAM using Sky130" happening on 9th April, 6pm IST. This session is LIVE and FREE.
Published: Mon, 04/05/21
Hi Did it ever occur, how complicated were the above IPs were to build from scratch? Did you know, it takes a year or so to get to basics before…
Published: Fri, 04/02/21
Hi 3-days left for OpenLANE/Sky130 Physical Design workshop registration to close Here's the link for more details:…
Published: Thu, 04/01/21
Hi You must be aware of amazing projects coming out of our e isting Hardware Design Programs. This is your chance to build something great, which is…
Published: Tue, 03/30/21
Hi We are glad to announce the launch of new (and the only) course on "Mi ed Signal Physical Design Labs" using OpenLANE RTL2GDS tool and Sky130…
Published: Tue, 03/30/21
Hi Here's VSD Internship first milestone - A 32kbits or 4kB SRAM compiled using open-source memory compiler OpenRAM and here is the GitHub Project…
Published: Mon, 03/29/21
Hi 7 Analog IP's and in-house standard cell library characterization engine - All in 10-weeks - Can you believe this? Find out by yourself from below…