Please find the details about Physical Design internships/Hardware Design Program.
 

 

LAST DATE TO APPLY - 5th April
 

Training (Week 1/2)

Week 1/2 - Advanced Physical Design using OpenLANE/Sky130

Dates – 7th April - 11th April

Registration link (workshop only) - https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/

Description – Once student completes basic chip Design flow using educational process development kits, they will be shifted to do a more advanced chip design environment, where students will have access to real chip manufacturing data from Google/Skywater 130nm process. With the announcement of Google-Skywater first manufacturable open source 130nm process design kit (pdk), open-source EDA world is no longer limited in scope to academic research and small-scale projects only. This along with the conception of OpenLANE flow, a fully-automated RTL2GDSII flow, has made the dream of “an IC for all” a near reality.

So, here is announcing the ultimate workshop on SoC design planning in OpenLANE flow using the latest Google-Skywater 130nm process node.
Goals to be achieved:

• Students will be able to design and characterize their own digital gates like Inverter
• Students will become independent enough to experiment with their own design
• Students will have an opportunity to interact with industry leaders in area of chip design and, if possible, manufacture their own chip after internship program

Online Hardware Design Program (Week 3 –  Week 10)

With opensource tools = ngspice, Magic, OpenLANE

Doing  project is the most important milestone in Engineer’s Professional career. Any individual getting to read for the Industry Career needs to embed few basic skills of project purpose understanding, planning, implementation, documentation, and execution stages. The below project is divided in different stages wherein student will undergo the same process followed in any corporate industry.

Week 3 - 10 – Project

Dates – As per internship dates (To know more about pricing, please drop us an email at vsd@vlsisystemdesign.com)

Project Execution Phases (VSD – 5stage process)

Understanding- Stage 1 – Week 2 – Literature Survey - What to do, why to do & How to do?

Planning and Implementation- Stage 2 – Week 3 & 4 – Circuit Design Implementation and pre-layout simulation

Documentations-Stage 3 – Week 5 – Report Submission standard VSD format which is like IEEE publication and many of the world-famous VLSI Journals.

Execution- Stage 4 – Week 6, 7, 8 – Layout implementation, Post-layout simulation, IP finishing and test commercial mixed signal RTL2GDS flow

Milestone -Stage 5 – Week 9, 10 – Final documentation, datasheet, report generation format

Project Areas (Students will be allotted project in one of below areas based on their performance in 2-weeks training):

1. RTL2GDS for mixed signal SoC (Inputs = mixed signal Verilog, open-source analog IP collaterals, access to commercial RTL2GDS toolchain, outputs = flow, GDSII)
2. Standard cell characterization flow using commercial spice simulators, layout tool and RTL2GDS suite
3. SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns
4. On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v
5. 10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference
6. 10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference
7. Comparator part of ADC
8. General purpose band-gap reference with N-well resistors at VDD=3.3v, Vbgp=1.2v

To know more about pricing, please drop us an email at vsd@vlsisystemdesign.com