Regular buffer v/s Clock buffer - Part 1
Published: Tue, 04/21/15
Hi Everyone, who's been a part of physical design or STA, must have definitely gone through this. When I thought about it, like 5 years back, as a…
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Published: Tue, 04/21/15
Hi Everyone, who's been a part of physical design or STA, must have definitely gone through this. When I thought about it, like 5 years back, as a…
Published: Wed, 04/15/15
Hey I realized last night, that I was celebrating my work anniversary. Thanks Linkedin for reminding me that :). And, thought, let's celebrate this…
Published: Mon, 04/13/15
Hey So, if these courses are the one's that gating the 'Physical Design Flow', learning cycle, then I've got great news for you. I published these…
Published: Sat, 04/11/15
Hi Hope you liked my previous post on "SPEF Format", and, there had been 4 days since my last post, so I believe the previous one is well absorbed.
Published: Mon, 04/06/15
Hey So, this has been due for long time. May be because of tight tape out deadlines, this very important piece of Physical Design flow just got…
Published: Sun, 04/05/15
Hi This is in continuation to the previous post, where I e plained about transistor level implementation of negative and positive latch. In this post,…
Published: Sat, 04/04/15
Hey Ever heard the saying "The early bird catches the worm?" So does the alert person seize great opportunities! I want to send a big THANK YOU to the…
Published: Fri, 04/03/15
Hi I have been receiving multiple queries on what is clk-to-q delay, how's it different from library setup time and library hold time, etc. I…
Published: Wed, 04/01/15
Hey Success! Over 60+ students have enrolled! Several fresher’s and e perts have completed the whole course along with solving real time issue faced…
Published: Mon, 03/30/15
Maze Routing - Lee's Algorithm Hi On the Lines followed by people all over the globe “Learn By Doing”, last week, I was browsing through the internet…