Mixed signal PD Webinar - Meeting invites
Published: Thu, 03/25/21
Hi This is regarding below email which was sent yesterday, meeting invites has been sent to everyone who has filled the form.. See you for an amazing…
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Webinar - Mixed Signal Physical Design labs using OpenLANE/Sky130
Published: Thu, 03/25/21
Hi Do you want to witness what VSD Interns are capable of? Then join Mi ed signal Physical Design labs using OpenLANE/Sky130 webinar on 26th March,…
Webinar - Mixed Signal Physical Design labs using OpenLANE/Sky130
Published: Wed, 03/24/21
Hi Do you want to witness what VSD Interns are capable of? Then join Mi ed signal Physical Design labs using OpenLANE/Sky130 webinar on 26th March,…
Final 4 hours - So What after you clear RISC-V Workshop?
Published: Mon, 03/22/21
Hi This workshop is Stage 0 in above image - A Qualification Criteria for you to enroll into our high intensity, critically acclaimed RISC-V based…
Registration for RISC-V based MYTH Workshop Closes in 14hours
Published: Mon, 03/22/21
Hi Registration for RISC-V based MYTH Workshop Closes in 14hours - The only workshop which covers RISC-V ISA and micro-architecture design in 5-days.
RISC-V meet-up just ended. It was amazing
Published: Sat, 03/20/21
Hi It was an amazing meetup session on RISC-V. Sharing snapshots from the call. Images speak for themselves Here's the link for 5-day RISC-V based…
Enough RISC-V jobs, but shortage of right talent
Published: Thu, 03/18/21
Don't believe me? Hear it straight from frequent RISC-V technical interviewers in a 30-min webinar on 20th March'2021, 7pm-7:30pm IST. Fill up below…
All about "effective" RISC-V trainings and VLSI internships
Published: Wed, 03/17/21
Hi How to do effective 5-day RISC-V trainings that your RISC-V core gets listed on RISC-V organization? How to do effective Physical design, mi ed…
VSDOpen2020 - Nothing like this in open-source VLSI
Published: Fri, 03/12/21
Hi Finally the promo video for VSDOpen2020 is out. It was a very successful high intensity VLSI open-source online conference. Thanks to Mike Wishart…
What can I do in 5-day VSD Workshop? Learn TL-Verilog and RISC-V
Published: Thu, 03/11/21
Hi - By Shivam Potdar Looking for a RISC-V processor design? You would find one on GitHub within seconds :) You can build it too in upcoming RISC-V…