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Power aware clock tree synthesis - Part 4

Published: Tue, 10/13/15

Hi We were looking for a solution for below scenario, and you will be amazed to see, how an 'Universal Gate' solves the below problem (of-course, at…

Power aware clock tree synthesis - Part 3

Published: Mon, 10/05/15

Hi And here's the solution to the problem posted in my previous article. 'AND gate itself'. If you observe carefully, you tie one of the inputs of an…

Power aware clock tree synthesis - Part 2

Published: Tue, 09/29/15

Hi While trying to build a clock tree which is power aware, let's go back a step ahead and look, what are the top observations for a clock network,…

Power aware clock tree synthesis - Part 1

Published: Thu, 09/24/15

Hi How about saving some power for the below clock tree network ?It's tricky and if we go with the right approach, we might end up saving almost…

VLSI Academy - Learn from scratch

Published: Sat, 09/19/15

Hi I have been getting this query, about, how to learn VLSI topic (especially back-end) from scratch, and there you go. I have arranged the videos and…

VLSI Academy - Buy 1 get 4 free 'challenge'

Published: Thu, 09/03/15

Hi Do I sound like a sleazy salesperson who’s trying to make money? :)So before putting this mail to your SPAM bo es, hear out the initiative and…

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