While you still decide to
take my layout course or not, I would like to give you a glimpse of the above topic on euler's path and euler's circuit, and how are they closely related to the pull-down and pull-up network of CMOS logic circuits
Have a look into the below network and let's assume that the red-spot is startpoint:
What we will do it, start from this red-spot and travel to some other spot (called as vertex) while making sure we use each edge exactly once. Look at below image for eg.
And we keep doing this, till we reach a certain endpoint or finish point, while covering each edge exactly once, like below
You can follow the arrow directions to confirm that we traversed to each edge exactly once.
This brings us to the classic definition of Euler's path, which is a path that includes all edges exactly once and
has different start and end vertices as below:
Very soon through my blogs and my course, this will be evident, that euler's path is the one that forms most of the pull-down network of a CMOS logic layout
Keep following.....
Let's take a moment of break here for you to grasp what we have written in this blog, while keeping you excited for how is above image related to drawing some of the complex layouts you must have thought of....
Remember what Rosalyn S. Yalow said about youths "The excitement of learning separates youth from old age. As long as you're learning, you're not old"
So be excited, be young and I will see you in my course...happy learning...
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