Generated clock & master clock ... Let's make it simple!! - Part 3

Published: Wed, 06/01/16

Hi

So now that you get the point of generated clocks in previous Part 1 and Part 2 of this post, now let’s conclude this by waveform derivation, means, suppose you are being given a generated clock table and now you want to derive the clock waveform out of it, how do you do it. Its very very simple if you have gone through my previous posts. Let’s assume that, and begin with below simple example of waveform table (by the way, this is a very classic interview question in semiconductor industries. Also, this technique is used to debug complex clock constraints in industries)

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So the above table, says, the first rise edge of the generated clock arrives at 2nd edge of master clock (remember, it doesn’t matter whether 2nd edge of master clock is a rise or fall), the first fall edge of generated clock arrives at 4th edge of master clock and second rise edge comes at 6th edge of master clock and below is how your generated clock will look like

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Let’s put this to test. How about everything else in above table remains the same, but the also the inverted is ‘ticked’, then the same gen clock will look something like below. Also, there is a trick that can be done to define the below gen clock. i.e……..(sentence continued after below image)

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(….sentence continued from above image) the same gen_clock’ can be defined using just the edges, and removing options of the table. And below is how the generated clock definition will look like for gen_clock’

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And finally, lets look into a more complex table like below, where we have the generated clock edges coming in middle of clock edges at some ‘t’ time units

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This is a classic example of how ‘edge’ and ‘shifted edge’ option of generated clock can be used in conjunction. Let’s the first fall edge is in middle of 2ns and 4ns i.e. at 3ns
So this is how you will define the generated clocks

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You will say, the first clock edge of generated clock arrives at 1st edge of master clock, and shifted by 0ns from 1st edge (Hence you see the first element in ‘shifted edge’ at ‘0’). Next …(and quite important one)… the first fall edge of generated clock arrives at 2nd edge of master clock, but shifted by 1ns from 2nd edge of master clock. So 2nd edge of master clock is at 2ns and generated clock is shifted by 1ns (i.e. arrives at 3ns) from 2nd edge. Makes sense…If not, I would suggest you to read the above sentence again. And the second rise edge of generated clock arrives at 5th edge of master clock. Hence you see the elements (0, 1, 0) in ns in the shifted edge row

This marks the end of all posts related to ‘Generated clock and master clock – Lets make it simple’. I hope these small posts (Part1, Part2 and Part3) will now give you a different view towards generated clocks and would help you achieve bigger and greater results

“Great things are not done by impulse, but by a series of small things brought together” – Vincent Van Gogh

Stay tuned for my new posts, and happy learning

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Static timing analysis:

Physical design flow

Circuit design and SPICE simulations – Part 1

Circuit design and SPICE simulations – Part 2

Clock tree synthesis – Part 1

Clock tree synthesis – Part 2

Signal integrity