A,B,C....Z

Published: Mon, 11/16/15

And, theoretically, I mean it…. OR at least I am on right track

So, last night, I recorded my last video on Circuit design and SPICE simulations, which marked the end of 5^th course on Udemy.

Now, why A,B,C,…Z? I meant about A to Z knowledge of Physical Design flow, which, I think is not complete without the knowledge and information on how MOSFET’s work, and that’s exactly has been my journey of making 5 courses that connect Physical design flow to MOSFET in an unique way….

If I ask someone, what completes Physical design flow knowledge, the common answers that I hear is clock tree synthesis, crosstalk, STA, DRC, LVS, route, post-route, etc.

I would say, the knowledge is incomplete, unless you know how a MOSFET works. And, with the help of all my 5 courses, I was able to connect physical design flow to MOSFET

Do you want to know what ‘real’ physical design flow is?

I would suggest you to take my courses in the below order and have a look into curriculum.

Circuit design and SPICE simulations:

Section 1: Introduction to circuit design and SPICE simulations

Section 2: NMOS Resistive region and saturation region of operation

Section 3: Introduction to SPICE

Section 4: SPICE simulation for lower nodes and velocity saturation effect

Section 5: CMOS voltage transfer characteristics

Section 6: Voltage Transfer Characteristics - SPICE simulations

Section 7: Static behavior Evaluation : CMOS inverter Robustness - Switching Threshold

Section 8: Static behavior Evaluation : CMOS inverter Robustness - Noise Margin

Section 9: Static behavior Evaluation : CMOS inverter Robustness - Power supply variation

Section 10: Static behavior Evaluation : CMOS inverter Robustness - Device variation

Physical design flow:

Section 1: Physical Design Flow Overview

Section 2: Floorplanning

Section 3: Placement

Section 4: Timing Analysis With Ideal Clocks

Section 5: Clock Tree Synthesis And Signal Integrity

Section 6: Routing And Design Rule Check (DRC)

Section 7: Parasitics Extraction

Clock tree synthesis:

Section 1: INTRODUCTION

Section 2: Clock Tree Quality Check Parameters

Section 3: H – Tree

Section 4: Clock Tree Modelling and Observations

Section 5: Buffered H – Tree

Section 6: Clock Tree Optimization Checklist

Section 7: Uneven Spread of Clock Endpoints

Section 8: Power Aware Clock Tree Synthesis

Section 9: Static Timing Analysis

Section 10: Summary

Signal integrity and crosstalk:

Section 1: Introduction

Section 2: Crosstalk - Why and How Crosstalk occurs in a CHIP ??

Section 3: Glitch Examples And Factors Affecting Glitch Height

Section 4: Tolerable Glitch Heights and Introduction to AC Noise Margin

Section 5: Timing Windows

Section 6: Crosstalk Delta Delay Analysis

Section 7: Noise Protection Technique

Section 8: Power Supply Noise And Power Mesh Solution

Section 9: Summary

VLSI – Essential concepts and detailed interview guide:

GENERATED CLOCKS DEFINITION AND CREATION

ON-CHIP VARIATION (OCV)

SETUP & HOLD TIMING ANALYSIS

OCV TIMING AND PESSIMISM REMOVAL

With all above sections, related to a Physical Design Flow, I can guarantee anyone taking all above 5 courses, should get a huge jump-start or even excel in semi-conductor industry

Stay focused!! Stay Tuned! For my new courses on LVS, DRC, and dynamic simulations

Happy Learning