Till now, I have written multiple blogs, but got this huge response of how great it would be to have all of them in form of power point presentations.

So there you go.... Below is the slide-share link where I have converted and uploaded my blogs in form of presentations in the best readable format you have ever noticed. Also, topics covered are the most demanding ones

http://www.slideshare.net/kunalghoshvlsisystem/presentations

A quick glance on the list of topics I have already uploaded are as below:

Clk-to-q delay, library setup and hold time

I have been receiving multiple queries on what is clk-to-q delay, how's it different from library setup time and library hold time, etc. I mentioned in my discussions, that the videos on CMOS digital circuit will be uploaded soon, but looks like, it might take some time, and hence decided to uploaded few images from my CMOS course, to explain the difference between all of them.

SPEF format

So, this has been due for long time. May be because of tight tape out deadlines, this very important piece of Physical Design flow just got missed. And I am sure, like me, many might be curious to know what is the IEEE SPEF format, what does various attributes of SPEF file represent, etc...

Regular buffer v/s Clock buffer

Everyone, who's been a part of physical design or STA, must have definitely gone through this. When I thought about it, like 5 years back, as a fresher, I really wished, somebody could had explained me this one in a much better way, with images.

I believe "A picture is worth a thousand words" :)

On-Chip Variation

Ever thought what's an interviewer's favorite questions to rip you off - all of my previous post :).

And On-Chip Variation (OCV) is one of them, specifically for Static Timing Analysis interview. This analysis is coming from people who got interviewed and recruited into leading VLSI industries.

Most importantly, my posts and videos have helped most of them and I really feel proud about it. Nice feeling.

Common clock path pessimism removal

Let me quote "Winston S Churchill", who said “A pessimist sees the difficulty in every opportunity; an optimist sees the opportunity in every difficulty.”

So pessimism is not good, and so is true for a timing path as well. :) With On-Chip variation, we might introduce extra pessimism in clock path, common to launch and capture flop clock pins. How? I will get back to this in below post (or may be next one). Our job, is to remove this pessimism and make a timing path analysis, close to a real one. How? I will get back to this, as well, in follow-up post

Signal Integrity (SI glitch)

Ahhh.... It's a pain ... right !! I can tell you exactly, why the above happens. Stay with me!!

On a circuit, fabricated on silicon, there are trillions of wires packed in a small area, something like below, and as me and you demand for higher speed and huge number of applications, poor engineers [:(] try to pack even more devices and wires in that tiny area

The Big Question

I was overwhelmed by the very common question being asked to me after my previous post, and these were from all levels of people (even people from verification and embedded background). "Why do we need to learn SPICE?"
And, that was exactly what I was expecting. "For the things we have to learn before we can do them, we learn by doing them". Though, this will be discussed in detail in my upcoming course of SPICE, let me try to give a glimpse of it here itself

Circuit design & SPICE simulations

You would be a bit surprised to see, that within few days, this course crossed more than 50 people and has great reviews already. You will be more surprised to see that, in contrast to my previous courses, I am offering this course at $11. Why did I do so? There's lot of thought that went behind this, and one of them is to give something back to the community. I know, what would be the next question, that will pop-up in your mind. Why even $11? Why not free? Well, write to me, and I will let you know the thought behind this as well :)

Happy Learning!!