Hi
And I am talking about 'velocity saturation' - a well-known short channel effect. If you observe below 2 graphs, with same (W/L) ratio, but at 2 different technology nodes, one has a quadratic dependence
on gate voltage and other has a linear dependence Note : These are snippets from my latest pre-launched course on 'Circuit Design & SPICE
simulations'
So, with increasing drain-to-source voltage (Vds), at any constant gate-to-source voltage (Vgs) (greater than threshold voltage of NMOS), the device at lower nodes (<250nm) tends to saturate early. As a result, you will
observe, that with increasing gate-source voltage, the increase in drain current is no more quadratic, but a linear function of gate-source voltage. To understand, I plotted below Ids v/s Vgs graphs for 2 different technology nodes in SPICE, and results were quite evident The reason for the above, is 'velocity saturation'. Below image captures most of it And, here's the fun part of my Circuit Design course, while you learn the above concepts, I will also show you a way of how to practically simulate it using SPICE engine and observe the effects by yourself. For those,
curious to learn about 'velocity saturation', I would like to quote "Curiosity is the spark behind the spark of every great idea. The future belongs to the curious" So join-in and learn everything you need to know about lower technology nodes and SPICE simulations Thanks Kunal (http://vlsisystemdesign.com/) |
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