Last 12hrs - Final call for PLL 1-day tutorial

Published: Sun, 10/17/21

Time Left for workshop registration - Last 12hrs

Course Curriculum-

Introduction – Basics of IP, ASIC Design flow, On-chip clock Multiplier, PLL,
Theory & fundamental Concepts – CMOS implementation, transistor sizing, 2nd order control system, IC fab process, Euler path.
Pre-layout Implementation (lab session) – setting up system with linux, installation of tools, IP design, simulation & verification
Post-layout Implementation (lab session) – device to block level layout, extracting parasitic capacitors, simulation & verification.
Summary & Conclusion – Review Results, Future work, Acknowledgement.

Features - Low cost ($10), 1-day, cloud lab based workshop

Timings - You can login at your own convenient time during 24-hrs duration of the workshop and start with lectures/labs at your own pace

Workshop Start date - 18th October, 11:59pm IST

Workshop End date - 19th October, 11:59pm IST

Registration link-

Indian Participants-

https://pages.razorpay.com/pllosu180

International Participants-

https://pages.razorpay.com/plldollar

All the best and happy learning

Other VSDOpen tutorials

https://www.vlsisystemdesign.com/registration/