Published: Tue, 08/31/21
14hrs left to get all my online VLSI courses between Rs. 360 to Rs. 525 price range. Below are the links for the same
All VLSI courses using FPGAs and Skywater 130nm PDKs
VSD – Mixed signal RISC-V based SoC on FPGA
https://www.udemy.com/course/vsd-mixed-signal-risc-v-based-soc-on-fpga/?couponCode=EDC502991593964E30E7
VSD Intern – Mixed Signal Physical Design flow with OpenLANE/Sky130
https://www.udemy.com/course/vsd-intern-mixed-signal-physical-design-flow/?couponCode=E4914BB30C983A919C28
VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130
https://www.udemy.com/course/vsd-intern-openram-configuration-for-4kb-sram-using-sky130/?couponCode=2671013F4E00F5531F08
VSD Intern – Analog Bandgap Reference design usingSky130
https://www.udemy.com/course/vsd-intern-analog-bandgap-reference-design-using-sky130/?couponCode=5E52F520B7A23AF0A02B
VSD Intern – Analog comparator design usingSky130
https://www.udemy.com/course/vsd-intern-analog-comparator-design-using-sky130/?couponCode=E545B313A4C2439BE0E3
VSD Intern - DAC IP design using Sky130 PDKs - Part 1 (specifications)
https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-1/?couponCode=A6385715606FD43471DE
VSD Intern - DAC IP design using Sky130 PDKs - Part 2 (circuit design)
https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-2/?couponCode=9AAF31B41A958A8463CC
VSD Intern - DAC IP design using Sky130 PDKs - Part 3 (layout)
https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-3/?couponCode=EBEAC91798E4C10957CE
VSD Intern – 10-bit DAC design using eSim and Sky130
https://www.udemy.com/course/vsd-intern-10-bit-dac-design-using-esim-and-sky130/?couponCode=A02770A86EEBFAEB10F4
VLSI Backend fundamental courses
Physical design
https://www.udemy.com/course/vlsi-academy-physical-design-flow/?couponCode=FBC9AD620FCCEDC5D26F
Physical design webinar:
https://www.udemy.com/course/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=0B30105911840AB5696C
Clock tree synthesis – Part 1:
https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis/?couponCode=54037F3ED75BF686DACB
Clock tree synthesis – Part 2:
https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis-part2/?couponCode=2BCD7C4071845839C7E2
Signal Integrity:
https://www.udemy.com/course/vlsi-academy-crosstalk/?couponCode=BDF1D95D6648835F50CD
Static timing analysis – Part 1:
https://www.udemy.com/course/vlsi-academy-sta-checks/?couponCode=47341958EF7F9E9F44B7
Static timing analysis – Part 2:
https://www.udemy.com/course/vlsi-academy-sta-checks-2/?couponCode=30C60ED76DF37ED2ACD0
Timing ECO webinar:
https://www.udemy.com/course/vsd-timing-eco-engineering-change-order-webinar/?couponCode=E5E1C6952C76E02A755D
Circuit design and SPICE simulations – Part 1:
https://www.udemy.com/course/vlsi-academy-circuit-design/?couponCode=1A26DA49AF1995D39D16
Circuit design and SPICE simulations – Part 2:
https://www.udemy.com/course/vlsi-academy-circuit-design-part2/?couponCode=F435A5A5119724BF9FEE
Custom Layout:
https://www.udemy.com/course/vlsi-academy-custom-layout/?couponCode=2712090BA79D2F8670EE
Library characterization – Part 1:
https://www.udemy.com/course/vlsi-academy-library-characterization-part-1/?couponCode=1A0410DC8A2B8CF79746
Library characterization – Part 2:
https://www.udemy.com/course/vsd-library-characterization-and-modelling-part-2/?couponCode=DC1CD63B2EFCB7628672
TCL Scripting – Part 1:
https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert/?couponCode=B25884ACA17C1E7CD671
TCL Scripting – Part 2:
https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=C35B0518595B1C275291
RISC-V based theory and lab based online courses
RISC-V ISA:
https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=402B7192483E760E7F84
https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1b/?couponCode=643AD9CA4228082E5E50
RISC-V based SoC Design:
https://www.udemy.com/course/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=D19C24EA3CF5FC2712B1
RISC-V based Chip Physical Design:
https://www.udemy.com/course/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=3E42DB8F9BB584CF1719
RISC-V based core Pipeline design:
https://www.udemy.com/course/vsd-pipelining-risc-v-with-transaction-level-verilog/?couponCode=66F9F97B5EB335E43737
All the best. Do well and keep me posted on progress.
Will be happy to help
Thanks