Here are some fun facts about CMOS circuit design workshop
- It's the most ignored workshop by freshers
- It helps 90% of VLSI job recruitment starting from Physical design jobs to circuit design to layout design to low power design jobs
- You can do a lot just by controlling drain-to-source voltage and gate-to-source voltage
- This workshop is more than just inverter characteristics and threshold voltage
- This workshop is more about CMOS robustness and why it's the most powerful logic element for so many decades in semiconductors
- People who have written patents about CMOS logic still claim that they haven't fully understood CMOS, NMOS and PMOS
That's how important and critical this workshop is if -
- You are seriously looking for VLSI jobs, filing patents or writing research papers
- Be it RTL design interview, or Physical design or low power design or layout design, the more you are in control of you NMOS/PMOS and CMOS voltage levels, you are in
- A good interviewer from top VLSI design companies ask about CMOS even before interviewing the job description mentioned (at least 90% of interview questions are from this workshop)
- A good IP designer is in full control of CMOS bias voltages.
So if you are going for a VLSI interview or switching jobs into VLSI, and if you say you know everything about CMOS - I would say, Think Twice!!
Here's the registration link (Registration closes in 5 days) -
