Hi
Our 6th cohort of hardware design program starts in 2-days. There are many questions about what we actually do in our programs. Let me summarize and generalize various stages of the program
Stage 1 - Design RnD
1) Design selection and draft specification
Stage 2 - RTL design and Synthesis
2) RTL coding and functional simulation using iverilog and gtkwave
3) RTL synthesis and gate level simulation using Yosys and Skywater 0.13nm or LibreSilicon 1um technology node
Stage 3 - SoC and Physical Design
4) Pre-layout flat/hierarchical static timing analysis
5) Port/Pin placement, Macro/IP placement, Power routing, top level chip floor-planning using Magic/OpenLANE
6) Placement and post-placement timing analysis
7) Clock tree synthesis and clock timing analysis
8) Routing and post-layout static timing analysis
Stage 4 - Physical Verification
9) Advance to GDSII and tapeout stage
Stage 5 - Project report writing and VLSI Job resume preparation
10) Detailed GitHub project report writing
This is the only program, which allows you to chose your own mentors, who are quite well known for their own domains, work with them and get a virtual design company experience. This program is a replica of how industry delivers projects, so VSD will provide Work Experience Certificates to all participants who completes 10-weeks with us.
Here's the registration link which closes in next 48hours-
All the best and happy learning
Find your mentors below:
