Did you know?
If you look at the power of a set of hardware resources, whether SoC or fully integrated system, the power of hardware resources is NOT constant. If somebody tells you that it's a 3W chip, a low power designer would be like, "Huh, what is 3W? Is it average, RMS, peak, sustained peak, thermal design power?" You really need really categories power consumption
Low Power design really shakes up RTL design, verification and Physical design fundamentals and the approach with which we need to layout a chip. As you go low power, fundamentals of rails, domains, islands, isolation comes in a big way, thereby, changing our approach of RTL2GDS
I was lucky enough to get first hand information about this pretty soon in my career, and you can be lucky too
Get all (real) chip design information, especially, in areas of IOT, wearable, automotives, home appliances, from "Srikanth Jadcherla" ex-IIT Madras, ex-Intel, ex-Synopsys and recipient of Intel Achievement Award (IAA) for his work in the area of "Low Power Design".
Here's the registration link for the same (due to multiple requests, academic pricing 85% discount valid for 36 more hours)-
Thanks to Skywater 130nm opensource PDKs, we were able to design advanced low-power labs using ngspice and Sky130 pdks, which forms the basis of LP.
FYI - Don't be surprised, if our next internship programs focuses on providing different power reduction options for our own Sky130 analog IPS
