Miracles in VLSI/RISC-V - 36hours left for registration

Published: Sat, 11/14/20

I would like to bring into your notice a chain of miracles which happened this year in field of VLSI/RISC-V

Previous-

Undergraduates designing high quality open-source analog IP's, even before anyone else did this in VLSI industry
Undergraduates developing mixed sign SoC design flow using OpenLANE/Sky130 PDK's, even before anyone else thought about this in undustry
Undergraduates developing working standard cell design flow from scratch with Sky130 PDK's, even now some of experienced people are looking at it
Undergraduates developing their own RISC-V cores in just 5-days using TL-Verilog and Makerchip platform,

Latest-

13-year old Creates RISC-V core during 5-day "RISC-V based MYTH" workshop - UNBELIEVABLE

Isn't that really UNBELIEVABLE? Stay tuned to know more

You need to put the right technology into right hands. The just wait for wonders

36-hours left for Beginner Physical Design Workshop registration

https://www.vlsisystemdesign.com/riscv-based-soc/

There have been a lot of queries about why there are no openings in Physical Design and Industry looks only for 3+ experienced engineers. The above workshop will guide you to the answer. May be then you can start approaching and preparing in the right direction