This is how I learnt VLSI at IIT

Published: Mon, 10/26/20

Nothing is more expensive than a missed opportunity. Though this one will cost you $10, but the experience is priceless - Especially for 2nd, 3rd, Final year and Fresher engineering students looking forward to make a bright career in VLSI. Get to know how I was taught VLSI inside best universities of our country. All the best and happy learning. Here's the link for more details.

Presenting first workshop with Prof. V. Kamakoti from IIT Madras as Honorary Lecturer

Look below link for more details

https://www.vlsisystemdesign.com/digital-system-design-and-modelling-using-verilog/

Curriculum:

1-Day workshop with cloud based verilog labs

Basics of transistors and logic gates (1hour)
1. CMOS Transistor theory (PMOS/NMOS/MOS Layers)
2. Tx gates, inverter,
3. Logic switches (NAND/NOR gates)
4. Simulation using MOS primitives and iverilog simulator

Gate-level design and modelling (1hour 30min)
1. Basic pos-level latch using CMOS Transistors
2. Simulation of pos-level latch with blocks built using MOS primitives
3. Structural representation of circuit and systems (eg. 32/64-bit adder)
4. Parameterized simulation strategy of 32/64-bit adder

Sequential Circuit design (1hour 30min)
1. Design representation (block diagram, state diagram, timing diagram, circuit diagram, verilog)
2. State machine lab to count even and odd number of zero’s and one’s for a system
  Simulation hick-ups in above state-machine and need for hand-shaking protocols (request-ack, ready-valid signals)

NOTE - At the end of workshop, a very well-structured GitHub link for all above labs will be shared with all participants to practice after the workshop