32-bit adder tested - 4 hours left for registration

Published: Fri, 10/30/20

And we tested a 32-bit adder with a basic test-bench skeleton. So we mentioned, the upcoming workshop is purely for freshers, 2nd year, 3rd year and 4th year engineering students

Registration for "Digital System Design and modelling" workshop with Prof. Kamakoti from IIT Madras as Honorary Lecturer, closes in next 4 hours, so probably you have last few hours to listen and learn from best Professor of our country. Below link as registration details:

https://www.vlsisystemdesign.com/digital-system-design-and-modelling-using-verilog/

For others who have already registered, you will receive you login ID's by 31stOct, 8pm IST

All the best and happy learning