Before that, this is just a gentle reminder that there are only 72hours left before we close registration, and there are a couple of places left. Here's the registration link:
RECENTLY ASKED QUESTIONS ABOUT "DIGITAL SYSTEM DESIGN USING VERILOG" WORKSHOP:
What are the registration fees?
It's discounted to $10 ($150) as we want everyone to have access to Prof. Kamakoti's lectures and listen to best Professor of our country
Can I join at my convenient time?
Yes. The workshop is conducted on VSD-IAT cloud platform, which allows you to login at your convenient time within 24hrs from November 1, 00:00hrs IST to November 1, 11:59pm IST
I am a 2nd year engineering student. Can I join this workshop?
In our last RISC-V workshop, we had students as young as 8th Grade. So as long as you are looking forward to learning something new and making a bright career in the field of VLSI, you are welcome. This workshop is kept at a very very basic level, which Prof. Kamakoti makes sure basics are covered first. Look at curriculum in above registration link
Can experienced system designers join for refreshing concepts?
We would suggest you to refrain from joining this workshop, as it's especially designed only for freshers looking to Start in the field of VLSI. But, if you are looking to share your system design and verilog experience with students, then you are more than welcome to join
Can I access content after 1st November?
You will be given lifetime access to all verilog codes after the workshop. Access to videos and VSD-IAT platform will terminate on November 1, 11:59pm IST
Do I need to install any software or tools to do labs?
No. Labs will be done on VSD-IAT cloud platform. You will be given access to a Linux Terminal, which has all necessary tools installed. Post workshop, we will provide scripts to install all tools on your laptops so you can do all experiments on your laptop and revise
Let me know if you have more questions. We will generalize them and put it on our website
All the best and happy learning