Based on heavy request, we are glad to announce, that 3rd consecutive RISC-V based MYTH workshop will happen from 22nd Oct to 26th Oct, here's the link for the same:
Look at feedback from participants of previous batch:
"The only RISC-V training available on social platform, that focuses on u-architecture building. Mostly RISC-V trainings are available on FPGA"
"TL-Verilog has made RTL coding so interesting for novice students like me, that now I aim to become RTL architect"
"Seen so many RISC-V trainings on FPGA and verification. However, this the only one, where I learnt about ISA coding. Now my engineering subjects on computer architecture have become so lively"
"This training really surprises me, why are there not enough trainings on RISC-V u-arch. I googled, luckily found this one, enrolled and now I am more confident about RTL design fundamentals"
Yes, we did made sure that RISC-V based MYTH workshop strengthens your RTL design fundamentals and also, we did made sure RISC-V based MYTH's are no more MYTH's
Join in soon. Last 3 days left for registration. All the best and happy learning
