This is a friendly reminder about this month's 90% to 93% discounted coupon codes, which gives you lifetime access to high quality online VLSI courses at $6 or $7 (Rs.360 or Rs.455)
Here's the links (and the exact order in which you should be taking the courses):
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first,
Physical design
https://www.udemy.com/course/vlsi-academy-physical-design-flow/?couponCode=0150DDC8C9066D72094D
Physical design webinar:
https://www.udemy.com/course/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=CED2559A050379E72C72
Then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Clock tree synthesis:
https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis/?couponCode=9D2B15F8A822CF1C5A5A
https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis-part2/?couponCode=EB2A8EBCAFB8479BA94E
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them.
Signal Integrity:
https://www.udemy.com/course/vlsi-academy-crosstalk/?couponCode=9AD1F40D183476325DDC
Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Static timing analysis:
https://www.udemy.com/course/vlsi-academy-sta-checks/?couponCode=1E77780B0FB54D29D240
https://www.udemy.com/course/vlsi-academy-sta-checks-2/?couponCode=552D5CA4F7EC7D1D3929
Timing ECO webinar:
https://www.udemy.com/course/vsd-timing-eco-engineering-change-order-webinar/?couponCode=C1D07CF187683DAA7D8E
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
Circuit design and SPICE simulations:
https://www.udemy.com/course/vlsi-academy-circuit-design/?couponCode=CBE3A12D5B0EB6C7A7F8
https://www.udemy.com/course/vlsi-academy-circuit-design-part2/?couponCode=5EAC4B598C00757F8D3B
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
Custom Layout:
https://www.udemy.com/course/vlsi-academy-custom-layout/?couponCode=91B91CAF89749C35331E
Library characterization:
https://www.udemy.com/course/vlsi-academy-library-characterization-part-1/?couponCode=DF99624A0ED7A52B0892
All above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So, for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
TCL Scripting:
https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert/?couponCode=F27C11D47A599FD54DEA
https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=A5EE8F5F0C9D78669681
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
RISC-V ISA:
https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=85A88902E0258D1023D3
https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1b/?couponCode=082B2347332DEF10AAF8
RISC-V based SoC Design:
https://www.udemy.com/course/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=AC3C90A12BC364899156
RISC-V based Chip Physical Design:
https://www.udemy.com/course/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=0FC014BFFAA28D2DDE50
RISC-V based core Pipeline design:
https://www.udemy.com/course/vsd-pipelining-risc-v-with-transaction-level-verilog/?couponCode=989A199B30D3F4358EED
All the best. Do well and keep me posted on progress
Thanks