So what are the ingredients of a high intensity 5-days hands-on RISC-V workshop are below web-based easy-to-use components-

1) HDL with timing abstract support (TL-Verilog/Makerchip by Steve Hoover, Redwood EDA)

2) Assessment platform (Jnaapti by Gautham Pai )

3) 14hrs per day for straight 8-months of content prep

4) And super charged participants

And what's the output of this workshop? Below image speaks it all. This is first ever workshop on globe where students (as junior as 2nd Year Engineering) have designed basic RISC-V pipe-lined CPU in span of 5-days, while taking into consideration of control, rd-after-write hazards using branches, register file bypass technique.

Pipe-lining lab started with implementing 3-cycle RISC-V. And on 5th day, the next thing, they wanted to do, was branch-predictors, and that feedback was beyond our expectations.

For all participants - We can proudly say that, after this 5-day workshop, (quoting Steve Hoover ) "You are not just learning the industry.....you are leading it"

Let's take a moment to congratulate all participants on taking up this challenge and completing this workshop successfully. Below link has more details

 

https://www.linkedin.com/posts/kunal-ghosh-vlsisystemdesign-com-28084836_ingredients-of-a-high-intensity-5-days-hands-on-activity-6695893468738387968-njdq