Hi

 

News 1:

Close to 3.4k people enrolled in VSD online VLSI courses in month of April alone. This is a clear message by people around the world that, whatsoever comes, we won't stop learning...It reminds me of a basic quote which our parents used to whisper in our years "Knowledge is Power". It indeed is... I can't Thank Everyone personally, but whoever reading this, I would like to Thank You for being a part of VSD community. Keep learning. Make the best use of this precious lock-down time. We can't change what comes tomorrow, but you can definitely change this current moment....

 

News 2:

In my last email, I had mentioned there might be a change in Udemy online VLSI courses. You might see a slight increase in price. I have saved one below coupon for each course which my last coupon for lowest price

 

You might want to enroll using below lowest price or new price - Up to you

Anyone looking forward for VLSI online courses, please don’t hesitate to forward this email

Below are keywords, which you want to learn, and their respective coupon links:

Keywords – skew, pulse-width, latency, clock power, clock buffer vs regular buffer, leakage and short circuit current, clock gating

Clock tree synthesis – Part 1 & 2:

https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis/?couponCode=177B1EF438162E6667EC

https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis-part2/?couponCode=634783D4A585BA3E758D

 

Keywords – lateral capacitance, noise margin, crosstalk, safe/unsafe glitch, aggressor, victim, ac noise margin, timing window, shielding, power supply noise, voltage droop, ground bounce

Signal integrity:

https://www.udemy.com/course/vlsi-academy-crosstalk/?couponCode=418DA801959788BDC3A9

 

Keywords – Floorplanning, placement optimization, utilization factor, aspect ratio, decoupling capacitor, pre-layout and post-layout timing analysis, multiple clock timing analysis, Maze lee’s routing algorithm, IEEE SPEF format

Physical design:

https://www.udemy.com/course/vlsi-academy-physical-design-flow/?couponCode=1FD23229E2FEC406A467

Physical design webinar:

https://www.udemy.com/course/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=B5F2B20355E64A808466

 

Keywords – PMOS, NMOS, SPICE simulations, Vt, drift current, pinch-off region, resistive operation, technology parameters, CMOS VTC, noise margin derivation, power supply variation, on-chip variation (OCV)

Circuit design and SPICE simulations – Part 1 & 2:

https://www.udemy.com/course/vlsi-academy-circuit-design/?couponCode=FC892B8C84148A8484E3

https://www.udemy.com/course/vlsi-academy-circuit-design-part2/?couponCode=28E7E9F9F802C690594D

 

Keywords – add_buffer, size_cell, Vt-swap, DRV, setup & hold fixing strategies, PBA, latch timing, jitter, CPPR, reg2reg analysis, interface analysis, clock-gating analysis, ICG, asynchronous checks

STA part 1 & 2:

https://www.udemy.com/course/vlsi-academy-sta-checks/?couponCode=890EDE0DD2D8472FE62F

https://www.udemy.com/course/vlsi-academy-sta-checks-2/?couponCode=56E6599B2FE1D2F3E1A0

STA webinar:

https://www.udemy.com/course/vsd-static-timing-analysis-sta-webinar/?couponCode=C5778E507FEEB35F1F99

Timing ECO:

https://www.udemy.com/course/vsd-timing-eco-engineering-change-order-webinar/?couponCode=BE290D963765D006A92B

 

Keywords – n-well, p-well, source, gate, drain formation, poly, stick-diagram, layout, drc rules, propagation delay, CCS-Timing, NLDM, ECSM, library setup/hold time, CCS-Noise, power characterization

Custom layout:

https://www.udemy.com/course/vlsi-academy-custom-layout/?couponCode=30DCC02AB1333F4C4C72

Library characterization:

https://www.udemy.com/course/vlsi-academy-library-characterization-part-1/?couponCode=59F722CDFCDCCF309A06

 

Keywords – tcl programming, eda, cad, variables, matrix, error handling, set_multi_cpu_usage

TCL Programming – Part 1 & 2:

https://www.udemy.com/course/vlsi-academy-library-characterization-part-1/?couponCode=59F722CDFCDCCF309A06

https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=12CEEEE01A282D82D333

 

Keywords – RISCV, signed/unsigned, ABI, doublewords, overflow, RV64IM, IEE754 floating point, pads, memory mapping, pipelining, SoC design, physical design implementation

RISCV- ISA – Part 1a & 1b:

https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=C2697763AA4690139604

https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1b/?couponCode=C72961F7BA8CBCC0F04A

Pipelining RISC-V using TL-verilog:

https://www.udemy.com/course/vsd-pipelining-risc-v-with-transaction-level-verilog/?couponCode=C01294AF7F0470116367

RISC-V SoC Design:

https://www.udemy.com/course/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=7133483A3AC9252854D2

RISC-V SoC Implementation:

https://www.udemy.com/course/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=A085BD58353B28E5E98E

 

Keywords – functional simulation, moore’s law, emulation, multi-core, multi-threading, hardware accelerators, avst_keccak, machine intelligence, regression model, wire error model, WiCE labs, binary classification

Embedded UVM:

https://www.udemy.com/course/vsd-embedded-uvm/?couponCode=CB354C98BC7100C47800

Functional Verification using E-UVM – Part 1:

https://www.udemy.com/course/functional-verification-using-embedded-uvm-part-1/?couponCode=70201C41ED50815E9117

Machine Intelligence in EDA/CAD:

https://www.udemy.com/course/vsd-machine-intelligence-in-eda-cad/?couponCode=09908E1CAE33FC0B9948