Day 1

Aim:  Introduction to Discrete Event Simulation Technology, Verilog, and Functional Verification, Getting acquainted with Simulation Tools (Theory – 4 hours, Lab – 2 hours)

• SoC design flow, role of Functional Verification
• Logic Modeling, Introduction to Verilog
• Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
• Simulation Technology, Discrete Event Simulation
• Verification Trends and Challenges
• Concepts and Principles of Functional Verification
• Testbench Architecture and Components
• Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms

Day 2

Aim:  Data Communication in Hardware, Bus functional models, Types of Hardware Buses (Serial, Memory Mapped, Streaming), UVM report mechanism (Theory – 3 hours, Lab – 3 hours)

• Verilog Ports
• Serial Buses – Overview of SPI and I2C
• Memory Mapped Buses – APB, AHB, Avalon-MM, AXI – Concept of Data Burst Transfer
• Streaming Bus – Avalon-ST, AMBA Streaming Bus
• Drivers and Monitors in a Testbench – Writing Bus Functional Models
• Lab – A simple DuT with UVM testbench would be provided – Debug using UVM log reports,

 

Day 3

Aim:  Concepts of object-oriented programming, EUVM data types and program structure (Theory – 4 hours, Lab – 2 hours)

 

• Introduction to UVM, EUVM
• Data Types, Structs, Arrays, Queues, and Associative Arrays
• Randomization and Constraints – Constraint Solving – Coding efficient constraints
• Principles of Object-oriented Programming, Classes, Class Interfaces, Inheritance and Polymorphism
• Coding Reference Models in a Testbench
• Lab – SHA3 DuT with UVM testbench would be provided – Students would be asked to create new testcases and constraints

Day 4

Aim: UVM Phasing  and Objection mechanisms, TLM ,OOP Design Patterns (Template and Strategy) (Theory – 3 hours, Lab – 3 hours)

• Transaction Level Modeling
• UVM Transactions and Sequences
• Concepts of TLM Ports, and Connectivity
• OOP Design Patterns (Template and Strategy), strong fundamentals to understand UVM Phase and Objection mechanisms
• Lab – A complex testbench with Virtual Sequences – Creating and integrating new test sequences

Day 5

Aim:  Advanced UVM Concepts – Factory, Callbacks – OOP Design Patterns (Factory and Observer), Concepts of SoC Verification (Theory – 3 hour, Lab – 3 hours)

• OOP Design Patterns (Factory Pattern, and Observer Pattern)
• UVM Factory Registration, Factory Overrides
• UVM Callbacks, Error Injection
• SoC Verification
• Initializing DuT RAM contents
• Lab – Adding Factory Overrides, Callbacks