[Last 2 days] Functional Verification workshop - 14th to 18th Oct

[Last 2 days] Functional Verification workshop - 14th to 18th Oct - 5pm to 11pm IST

Published: Mon, 10/07/19

Thanks for attending the preliminary session. Please find the below link for registration details (Last date - 9th October): (As per request from participants, the timings for workshop has been finalized from 5pm to 11pm IST)

https://www.vlsisystemdesign.com/upcoming-event/

Course Contents:

Day 1: Introduction to Discrete Event Simulation Technology, Verilog, and Functional Verification, Getting acquainted with Simulation Tools (Theory– 4 hours, Lab– 2 hours)
Day 2: Data Communication in Hardware, Bus functional models, Types of Hardware Buses (Serial, Memory Mapped, Streaming), UVM report mechanism (Theory– 3 hours, Lab– 3 hours)
Day 3: Concepts of object-oriented programming, EUVM data types and program structure (Theory– 4 hours, Lab– 2 hours)
Day 4:UVM Phasing and Objection mechanisms, TLM ,OOP Design Patterns (Template and Strategy) (Theory– 3 hours, Lab– 3 hours)
Day 5: Advanced UVM Concepts – Factory, Callbacks – OOP Design Patterns (Factory and Observer), Concepts of SoC Verification (Theory– 3 hour, Lab– 3 hours)

Thanks