I had been re-iterating my tips for strategic VLSI learning multiple times and in multiple ways. Finally, we have proven that through most recent “VLSI open-source EDA Online workshop” conducted from 23^rd September to 27^th September

Three people, without whom this workshop would have been impossible:

1. Naveed Sherwani – President & CEO SiFive
2. Jack Kang – VP Sales, SiFive
3. Tim Edwards – SVP Analog Platform, efabless

Without SiFive’s E31 RISC-V core for final project work, and Tim’s open-source EDA tool chain, this workshop would have been practically impossible to conduct at less than $50/student for 5-days. Moreover trainings, I believe, should make everyone think with an open mind, which is possible when you are told to build something with very limited resources.

AND THAT’S WHAT EXACTLY HAPPENED – Around 200 students around the globe, explored (and are still exploring) open-source EDA tools for learning complex topics of VLSI.

That was our end goal, and thanks to open-mindedness of all 200 participants, we all were able to achieve them. I will very soon post all participants scoreboard and you can check for yourself, how brilliantly students have characterized some critical blocks of SiFive RISC-V core E31 and came up with very good solutions for initial densities and aspect ratio

Finally, the tips which I have been iterating many times in past, is same as below, which was exactly followed by all students. Re-iterating it again below along with 90% discount links for 24 hours

Tips on order in which you need to learn VLSI and become a CHAMPION:

If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first,

 

Physical design

https://www.udemy.com/course/vlsi-academy-physical-design-flow/?couponCode=ITS_PROVEN

 

Physical design webinar:

https://www.udemy.com/course/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=ITS_PROVEN

 

Then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.

Clock tree synthesis:

https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis/?couponCode=ITS_PROVEN

 

https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis-part2/?couponCode=ITS_PROVEN

 

Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them.

 

Signal Integrity:

https://www.udemy.com/course/vlsi-academy-crosstalk/?couponCode=ITS_PROVEN

 

Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2  and Timing ECO webinar courses, respectively

 

Static timing analysis:

https://www.udemy.com/course/vlsi-academy-sta-checks/?couponCode=ITS_PROVEN

 

https://www.udemy.com/course/vlsi-academy-sta-checks-2/?couponCode=ITS_PROVEN

 

Timing ECO webinar:

https://www.udemy.com/course/vsd-timing-eco-engineering-change-order-webinar/?couponCode=ITS_PROVEN

 

Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To fullfill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.

 

Circuit design and SPICE simulations:

https://www.udemy.com/course/vlsi-academy-circuit-design/?couponCode=ITS_PROVEN

 

https://www.udemy.com/course/vlsi-academy-circuit-design-part2/?couponCode=ITS_PROVEN

 

And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course

 

Custom Layout:

https://www.udemy.com/course/vlsi-academy-custom-layout/?couponCode=ITS_PROVEN

 

Library characterization:

https://www.udemy.com/course/vlsi-academy-library-characterization-part-1/?couponCode=ITS_PROVEN

 

All above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle

 

TCL Scripting:

https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert/?couponCode=ITS_PROVEN

 

https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=ITS_PROVEN

 

Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor 

 

RISC-V ISA:

https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=ITS_PROVEN

 

https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1b/?couponCode=ITS_PROVEN

 

All the best. Do well and keep me posted on progress

Thanks