Hi
Thanks for being a loyal email subscriber. We appreciate hearing from you. Let us know if you ever have any questions.
This is a gentle reminder that "Registration closes on 16th September", so this is the last week to register
Below link has details to register for the workshop
Below is the detailed content of the workshop.
Outcome of this workshop:
1) A ready made "Industry Level" guide for VLSI back-end job interviews and placements
2) Completion Certificate and Grading Certificate from EICT Academy, IIT Guwahati - One of top 7 institutes in India
In case of any queries, you might want to contact Prof. Gaurav Trivedi from IIT Guwahati Or Reply to this email and we will be happy to help
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Online (LIVE Streaming) Training Programme on “VLSI Chip Design Hands on using Open Source
EDA”
(23 – 27 September, 2019)
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Module
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Lecture
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Topics
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Tentative Speakers
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Module 01
SoC Planning
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Lecture 1
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Lecture 2
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SoC Design :
- RISC-V and picoSoC overview
- Overview about SoC planning, like placing pads, macros, memories and IP’s
- Overview about design cycle, like RTL synthesis, physical design, layout, DRC, clock tree synthesis and STA.
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Mr. Kunal P Ghosh
(Director, VSD Corp. Pvt. Ltd.)
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Module 02
Floor planning & timing analysis
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Lecture 3
&
Lecture 4
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Pre-layout timing analysis and
Floorplanning:
- Setup/Hold analysis (Theory +
Labs)
- Report nworst, timing_qor,
analysis_coverage in clock ideal mode (Theory + Labs)
- Aspect ratio, utilization factor, power
planning (Theory + Labs)
- Pre-placed cell tap cell, macro, memory/IP
placement (Theory + Labs)
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Mr. Kunal P Ghosh
(Director, VSD Corp. Pvt. Ltd.)
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Module 03
Placement, Clock tree synthesis
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Lecture 5
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Lecture 6
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Placement, Clock tree synthesis, Routing and SI (Lab – Yosys, Graywolf, Qrouter, OpenSTA,
MAGIC)
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- Placement STA with clock ideal (Theory + Labs)
- CTS quality check – skew, pulse width, duty cycle, latency (Theory + Labs)
- Routing quality check – signal integrity, delta delay, glitch (Theory + Labs)
- DRC, LVS check and fix (Theory + Labs)
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Mr. Kunal P Ghosh
(Director, VSD Corp. Pvt. Ltd.)
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Module 04
Global routing and Detailed routing
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Lecture 7
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Lecture 8
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Post-layout STA (Lab – OpenSTA)
- Types of setup/hold checks – reg2reg and IO, clock gating, recovery/removal, data-to-data, latch (time borrow/time given) (Theory + Labs)
- Need of library, advanced ccs/ecsm concepts, variation (OCV, AOCV, SOCV in brief)
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Mr. Kunal P Ghosh
(Director, VSD Corp. Pvt. Ltd.)
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Module 05
LIVE Project
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Lecture 9
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Lecture 10
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SiFive E31 design (Labs)
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- Perform RTL2GDS (including floor planning) of blocks within E31 design
- Pre-layout and post-layout timing analysis
- Evaluate block area
- Integration of al blocks on chip-top
- Project score analysis
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Mr. Kunal P Ghosh
(Director, VSD Corp. Pvt. Ltd.)
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