VSDOpen2018, the six hours program, responds to many trends and challenges in semiconductor design using open source hardware tools and developing the IP to reach the silicon level, with papers and presentation in the research paper sessions covering the core set of design topics: Front-end open-source EDA tool flows for IC design and verification, Clock tree synthesis and optimization of digital IC’s for best Performance, Floorplanning of digital IC’s for best area, Place and Route of digital IC’s for best PPA, Standard cell layout/characterization for compact area/high performance/minimal routing resources, Machine Learning in EDA.

Key highlights of this conference were:

1. Keynote by Prof. David Patterson on "A New Golden Age in Computer Architecture"

2. Keynote by Prof. Sharon Hu on "Professional growth with ACM SIGDA"

3. Keynote by Mohamed Kaseem on "Applying open community innovation to hardware product creation"

Apart from above keynotes, here are some interesting papers, on RISC-V and opensource EDA which were presented

1. TAU 2019 contest announcement by George Chen from Intel

2. Padframe generator for qflow (an opensource RTL2GDS tool) by Phillip Guhring, Vienna Austria

3. PNR of digital core IC using cloud based EDA tool by Anand Rajgopalan, Mumbai University

4. Coverage driven functional verification on RISC-V cores, by Lavanya J., Anmol Sahoo, Paul George from IIT Madras

5. Rapid Physical IC implementation and integration using efabless platform by Alberto Gomez Saiz, Imperial college, London

6. Introduction to TL-Verilog by Steve Hoover, Redwood EDA

7. Formally verifying WARP-V, an open-source TL-Verilog RISC-V Core generator by Akos Hadnagy, TU Delft

8. Top-down transaction level design with TL-Verilog by Ahmed Salman, Alexandria University