A quick gif snippet from my upcoming course on "RISC-V processor design"
If you care-fully look at the program counter at left and the assembly language program on top-right, there are so many things happening.
And guess what - "This is just the beginning" - no mux yet, no pipelines yet, no control unit yet.... They are all coming up....
Stay tuned for full course which will be updated in below link:
In case, you plan to take upcoming "RISC-V processor design", I would strongly suggest you understand the RISC-V ISA first, from below online courses:
RISC-V Part 1a (Basics and RV64 integer ISA):
RISC-V Part 1b (Single-Double precision floating point and Multiply/divide ISA):
