Really happy to see you have joined this group and are a part of the largest VLSI community of ~18000 people. As an initial help (and this is for all new people who have joined and missed my previous blogs), I would like to re-iterate my tips to learn VLSI and crack interviews.

This has helped candidates place in some Tier-1 companies and it might help you too…All you need to do is – Finish courses 100% in below order

VLSI Interview FAQ's (for quick revision before interviews):

https://www.udemy.com/vlsi-academy/?couponCode=REITERATE_MYTIPS

 

Machine intelligence in EDA/CAD (for advanced RND positions in EDA/CAD for VLSI):

https://www.udemy.com/vsd-machine-intelligence-in-eda-cad/?couponCode=REITERATE_MYTIPS

 

For RISC-V pipe-lining related positions:

https://www.udemy.com/vsd-pipelining-risc-v-with-transaction-level-verilog/?couponCode=REITERATE_MYTIPS

 

Tips on order in which you need to learn VLSI and become a CHAMPION (available at 90% discount for 15 hours):

If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to investigate details of how the clock is been built.

Physical design flow:

https://www.udemy.com/vlsi-academy-physical-design-flow/?couponCode=REITERATE_MYTIPS

Physical design labs:

https://www.udemy.com/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=REITERATE_MYTIPS

Clock tree synthesis – Part 1 & 2:

https://www.udemy.com/vlsi-academy-clock-tree-synthesis/?couponCode=REITERATE_MYTIPS

https://www.udemy.com/vlsi-academy-clock-tree-synthesis-part2/?couponCode=REITERATE_MYTIPS

Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively

Signal integrity:

https://www.udemy.com/vlsi-academy-crosstalk/?couponCode=REITERATE_MYTIPS

Static timing analysis – Part 1 & 2:

https://www.udemy.com/vlsi-academy-sta-checks/?couponCode=REITERATE_MYTIPS

https://www.udemy.com/vlsi-academy-sta-checks-2/?couponCode=REITERATE_MYTIPS

Static timing analysis – Webinar and Labs

https://www.udemy.com/vsd-static-timing-analysis-sta-webinar/?couponCode=REITERATE_MYTIPS

Timing ECO webinar:

https://www.udemy.com/vsd-timing-eco-engineering-change-order-webinar/?couponCode=REITERATE_MYTIPS

Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.

Circuit design and SPICE simulations – Part 1 & 2:

https://www.udemy.com/vlsi-academy-circuit-design/?couponCode=REITERATE_MYTIPS

https://www.udemy.com/vlsi-academy-circuit-design-part2/?couponCode=REITERATE_MYTIPS

And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course

Custom layout:

https://www.udemy.com/vlsi-academy-custom-layout/?couponCode=REITERATE_MYTIPS

Library characterization – Part 1 & 2:

https://www.udemy.com/vlsi-academy-library-characterization-part-1/?couponCode=REITERATE_MYTIPS

https://www.udemy.com/vsd-library-characterization-and-modelling-part-2/?couponCode=REITERATE_MYTIPS

All above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So, for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle

TCL scripting Part 1 & 2:

https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert/?couponCode=REITERATE_MYTIPS

https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=REITERATE_MYTIPS

Atlas, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor 

RISC-V ISA Part 1a & 1b:

https://www.udemy.com/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=REITERATE_MYTIPS

https://www.udemy.com/vsd-riscv-instruction-set-architecture-isa-part-1b/?couponCode=REITERATE_MYTIPS

The final nail to the coffin will be a RISC-V micro-processor project, and below 2 will help you through entire tape-out process:

Making Raven Chip – How to design a RISC-V SoC:

https://www.udemy.com/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=REITERATE_MYTIPS

SoC design of PicoRV32 RISC-V micro-processor:

https://www.udemy.com/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=REITERATE_MYTIPS

Connect with me for more guidance!!

Hope you enjoy the session best of luck for future!!