For last 2 months, we have been working hard to evaluate ‘vsdflow’ on RISC-V SHAKTI processor. Our initial results have been very promising, which made us to believe that we can tape-out 180nm process (target is 16nm) using opensource rtl-2-gds ‘vsdflow’.

(A prototype ‘vsdflow’ on github - https://github.com/kunalg123/vsdflow )

The vision –

Shakti project is a family of 6 processors based on RISC-V ISA - 3 base processors (E-class, C-class, I-class) and 3 multi-core processors (M-class, S-Class, H-class). E-class (low-end) cores use 3-stage pipe-line and available in 32-bit and 64-bit versions, that will run at 200MHz. C-class (high-end) cores use a 5-stage pipeline and target speeds up to 800MHz, which can be customized to run up to 2GHz.

VSD comes with 7+ years of experience in high-quality online VLSI training (~17000 people around 133 countries) and about 4+ years’ experience in design & EDA, from commercial to opensource. We have presented and tested this flow (not taped out) on small processors like picoSoC (24k instance count design) and E31 (60k instance count design).

This provides a unique opportunity for both entities to take up all existing taped-out cores and benchmark using ‘vsdflow’. We have planned atleast 6 tape-outs (mostly govt. projects, not official yet) for 2019, and if things go right, we will see at-most 6 tapeouts using ‘vsdflow’. It doesn’t stop there; the entire flow will be deployed to all engineering colleges using VSD’s online VLSI training infrastructure.  

With learning being online, SHAKTI core and ‘vsdflow’ being opensource, this is first-time in the history of VLSI design & EDA (thanks to RISC-V ecosystem and Shakti Team at IITM lead by Prof. Kamakoti), a chip will ever be taped-out using all opensource flow, which will cater to almost 80% Indian Semiconductor Market. We haven’t accounted for world market yet. It’s a serious business model. Shakti team and VSD have proved this business model in past, and we will continue doing so.

Imagine a student in some corner of the world learning processor design & verilog coding using target FPGA, and that FPGA board is built using all opensource tools…. He/She can learn and build his/her own FPGA board from scratch

A big cheer and Thanks to all below opensource developers from all over the world – This mission and vision would not have been possible without your years of dedication. We will not let you down….

Clifford Wolf

Dan Gisselquist

Tim Edwards

Tsung-Wei Hung

James Cherry

Mingyu Woo

Andrew Kahng

Rajeev Srivastava

Mateus Fogaça

Any questions, please feel free to drop in an email at vsd@vlsisytemdesign.com