Hi
Remember 'vsdflow' - which was part of IEEE, Semicon China and DAC US...
Its updated and now available for download for FREE...Here's the link:
'vsdflow' is also the best utility ever written for learning EDA based TCL scripting...Very hard to find a tool, with its detailed explanation in form of videos. 'vsdflow' is explained (in detail) in below 2 TCL scripting courses, so you might want to have a look:
TCL scripting part 1:
TCL scripting part 2:
This course has gone to a level, where I have heard managers in VLSI industries asking their team to learn TCL only
through this course and 'vsdflow'.
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is
synthesized (using Yosys).
The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, RISC-V picorv32, and can be further tested for multi-million instance count
using hierarchical or glue logic.
Some background about VLSI backend is needed for to understand 'vsdflow' operations, so here are 3 important courses: (check with your interviewer and they might recommend these courses):
Physical design flow:
Static timing analysis - Part 1:
Static timing analysis - Part 2:
There
you go...Write your first TCL script, learn it from basics to advanced to expert level, apply it from EDA perspective, and you are good to go for your job or interviews....
All the best and happy learning
